1. Field of the Invention
The present invention relates to a structure of a semiconductor device, and particularly to a structure of a buried word line.
2. Description of the Prior Art
As electronic products are becoming lighter, thinner, shorter, and smaller, dynamic random access memory (DRAM) geometries are being scaled down to match the trends of high integration and high density. DRAM composed of a lot of memory cells is one of the most popular volatile memory devices. Each memory cell of DRAM comprises a MOS (metal-oxide-semiconductor) transistor and at least a capacitor stacked each other in a series connection. By using word lines and bit lines, DRAM can be read and programmed.
In order to miniaturize DRAM, gate channel length is shortened, but the short channel effect becomes an obstacle to the improvement of the integration of the semiconductor device. Methods of avoiding the short channel effect had been proposed, for example, decreasing the thickness of the gate oxide layer, increasing dopant concentration, and the like. However, theses methods may encounter some problems, such as low element reliability and slow data transfer rates, and are unsuitable to be actually used.
In order to solve these problems, a hole type recess channel MOS transistor has been developed and gradually adopted to increase the integration. In comparison with a conventional horizontal MOS transistor, the hole type recess channel MOS transistor includes the gate and the source/drain formed in an etched trench of a semiconductor substrate, and furthermore, the gate channel region is disposed at the bottom portion of the trench, thereby to reduce the horizontal area of the MOS transistor for improving the device integration.
FIG. 1 illustrates a schematically cross-sectional view of a recess channel MOS transistor device having a gate structure and a word line structure thereabove, which is constructed in a semiconductor substrate 10. The MOS transistor includes a gate oxide layer 12, a polysilicon layer 14, a doped polysilicon layer 16, an inner spacer 18, a polysilicon layer 20, a tungsten metal layer 22, a silicon nitride layer 24, and spacers 26. The tungsten metal layer 22 serving as a word line is disposed above the surface of the semiconductor substrate 10.
To improve the integration of a semiconductor device is constantly a subject to be researched and developed, and, therefore, there is still a need for a novel MOS transistor device structure.